Circuit arrangements for switching a current driving a load on and off are known.
FIG. 1 shows such a circuit arrangement, which uses a transistor 20′ as a current source or current sink. The control electrode of the transistor 20′ is connected to a DC voltage source 80′. The current source 20′ is connected in series with a load 40′, for example with a laser diode. A switching transistor 50′, which is likewise connected in series with the current source 20′, is used as a switch for the current source. The switching transistor 50′, which is in the form of a field-effect transistor, for example, is connected by means of its gate electrode 51′ to a driving device which comprises the transistors 75′ and 70′, for example. The input 1 of the driving device 70′, 75′ has a switch-on/switch-off signal P applied to it, as illustrated in FIG. 2, for example. Between the gate 51′ and the drain electrode 52′ of the switching transistor 50′ there is a manufacture-dependent parasitic capacitance 60′, which is also known as the Miller capacitance. As will be explained later, this parasitic capacitance is the cause of overcurrents that are brought about when the current source 20′ is switched off. The gate/source voltage GS of the switching transistor 50′ controls the state of the switching transistor. If this gate/source voltage GS is lower than the threshold voltage of the switching transistor 50′, the current IL is interrupted by the switching transistor 50′. The gate/source voltage GS is S controlled by means of the driving device 70′, 75′. However, when the switching transistor 50′ and hence the current source 20′ are disconnected, an overcurrent, also called a current spike, is produced which has its origins in the parasitic capacitance 60′ of the switching transistor 50′. This is because a falling edge of the gate/source voltage GS on the switching transistor 50′ (the profile of said gate/source voltage being shown in FIG. 4) causes the parasitic capacitance 60′ to transfer the sudden voltage change on the control electrode 51′ to the output electrode 52′ of the switching transistor 50′ and to drive the transistor 20′ at a higher level. This causes an overcurrent through the load 40′, as shown in FIG. 3 at the time ta. The overcurrent flows until the parasitic capacitance's charge has been reversed. The time ta characterizes the time at which the switch-off signal is applied to the input 1 of the driving device 70′, 75′. In the case of certain applications, such current spikes can result in the load 40′ being destroyed, as can be the case with a laser diode, for example.